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ad7013 rev. a one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. cmos tia is-54 baseband receive port general description the ad7013 is a complete low power, cmos, tia is-54 base- band receive port with single +5 v power supply. the part is designed to perform the baseband conversion of i and q waveforms in accordance with the american (tia is-54) digital cellular telephone system. the receive path consists of two high performance sigma-delta adcs, each followed by a fir digital filter. a primary and auxiliary set of iq differential analog inputs are provided, where either can be selected as inputs to the sigma-delta adcs. also, a choice of two frequency responses are available for the receive fir filters; a root-raised-cosine filter for digital mode or a brick wall response for analog mode. differential analog inputs are provided for both i and q channels. on-chip calibration logic is also provided to remove either on-chip offsets or remove system offsets. a 16-bit serial interface is provided, interfacing easily to most dsps. the receive path also provides a means to vary the sampling instant, giving a resolution to 1/32 of a symbol interval. the auxiliary section provides two 8-bit dacs and one 10-bit dac for functions such as automatic gain control (agc), automatic frequency control (afc) and power amplifier control. as it is a necessity for all digital mobile systems to use the lowest possible power, the device has receive and auxiliary power down options. the ad7013 is housed in a space efficient 28-pin ssop (shrink small outline package). functional block diagram dxclk ad7013 v aa dgnd v dd agnd bypass mclk irx irx rx clk rx data rx frame aux dac1 aux dac2 aux dac3 d s d modulator aux irx aux irx qrx qrx aux qrx aux qrx mux mux data in frame in receive channel serial interface analog mode fir digital filter root raised cosine fir digital filter fs adjust agnd agnd mode1 frame out serial interface analog mode fir digital filter root raised cosine fir digital filter offset adjust offset adjust switched cap filter switched cap filter d s d modulator 1.23v reference latch 8-bit aux dac full-scale adjust latch 8-bit aux dac latch 10-bit aux dac features single +5 v supply receive channel differential or single-ended analog inputs auxiliary set of analog i & q inputs two sigma-delta a/d converters choice of two digital fir filters root-raised-cosine rx filters, a = 0.35 brick wall fir rx filters on-chip or user rx offset calibration adc sampling vernier three auxiliary dacs on-chip voltage reference low active power dissipation, typical 45 mw low sleep mode power dissipation, <50 m w 28-pin ssop applications american tia digital cellular telephony american analog cellular telephony digital baseband receivers
parameter ad7013a units test conditions/comments receive section adc specification number of input channels 4 (irxCirx) and qrxCqrx); cr12 = 0 (aux irxCaux irx) and (aux qrxCaux qrx); cr12 = 1 number of adc channels 2 resolution 15 bits adc signal range 2.6 volts p-p measured using an input sine wave of 3 khz differential signal range v bias 0.65 volts for both noninverting and inverting analog inputs single-ended signal range v bias 1.3 volts for noninverting analog inputs; inverting analog inputs = v bias v bias 0.65 to (v aa C0.65) volts min/max differential 1.3 to (v aa C1.3) volts min/max single-ended input range accuracy 7.5 % accuracy bias offset error 7.5 mv autocalibration; v bias = min/max 55 mv user calibration; i & q offset adjust registers equal to zero dynamic specifications cmrr C40 db typ measured using an input sine wave of 3 khz with both noninverting and inverting inputs tied together dynamic range 70 db typ digital mode filter; cr11 = 0 65 db typ analog mode filter; cr11 = 1 snr 2 65 db min digital mode filter; cr11 = 0 68 db typ 60 db min analog mode filter; cr11 = 1 63 db typ input sampling rate 1.5552/1.28 mhz mclk = 6.2208 mhz/5.12 mhz; mclk/4 output word rate 97.2/80 khz mclk = 6.2208 mhz/5.12 mhz; 4 sampling of the symbol rate, mclk/64 48.6/40 khz mclk = 6.2208 mhz/5.12 mhz; 2 sampling of the symbol rate, mclk/128 receive digital filters digital mode mclk = 6.2208 mhz root-raised-cosine a = 0.35 settling time 329.2 m s absolute group delay 164.6 m s frequency response 0C7.8975 khz 0.05 db max 11.9 khz C3.0 db 16.4025 khz C19 db > 30 khz C66 db max analog mode mclk = 5.12 mhz brick wall filter settling time 400 m s absolute group delay 200 m s frequency response 0C8 khz 0 to C0.5 db max 11.4 khz C3.0 db 15 khz C24 db >17 khz C68 db max tia is-54 receive specifications error vector magnitude 3 2 % rms typ measured using a full-scale input error offset magnitude 3 1 % rms typ (v aa = v dd = +5 v 10%; agnd = dgnd = 0 v; f mclk = 6.2208 mhz; t a = t min to t max , unless otherwise noted) C2C rev. a ad7013Cspecifications 1
parameter ad7013a units test conditions/comments auxiliary section aux dac1 aux dac2 aux dac3 resolution 10 8 8 bits dc accuracy integral 3 1 1 lsbs max differential C1.5/+4 1 1 lsbs max aux dac2 & aux dac3 guaranteed monotonic zero code leakage 500 500 500 na max gain error 7.5 7.5 7.5 % max output full-scale current 566 280 280 m ar set = 18 k w output impedance 4 2m w typ output voltage compliance 2.6 volts max coding binary power down option yes reference specifications v ref 1.23 volts typ reference accuracy 5 % max reference impedance 20 k w typ logic inputs v inh , input high voltage v dd C0.9 v min v inl , input low voltage 0.9 v max i inh , input current 10 m a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage v dd C0.4 v min |i out | 40 m a v ol , output low voltage 0.4 v max |i out | 1.6 ma power supplies v dd 4.5/5.5 v min /v max i dd 5 all sections active 10.5 ma max cr14 = cr15 = cr16 = cr17 = 1 9 ma typ mclk = 6.2208 mhz; 80 pf load on dxclk adcs active only 8.6 ma max cr14 = 1; cr15 = cr16 = cr17 = 0 mclk = 6.2208 mhz; 80 pf load on dxclk aux dacs active only 2.2 ma max cr14 = 0; cr15 = cr16 = cr17 = 1; mclk inactive, mclk = 0 v 10-bit aux dac active 1.6 ma max cr14 = cr15 = cr16 = 0; cr17 = 1; mclk inactive, mclk = 0 v all sections powered down 6 2 ma max cr14 = cr15 = cr16 = cr17 = 0 mclk = 6.2208 mhz; 80 pf load on dxclk 30 m a typ mclk =100 khz; 80 pf load on dxclk 10 m a max mclk inactive, mclk = 0 v notes 1 operating temperature ranges as follows: a version: C40 c to +85 c. 2 snr calculation includes noise and distortion components. 3 see terminology. 4 sampled tested only. 5 measured while the digital inputs are static and equal to 0 v or v dd . 6 with all sections powered down, i dd is proportional to the capacitive load on dxclk. for example, i dd is typically 1.7 ma with 80 pf load and 600 m a with 10 pf load. specifications subject to change without notice. C3C rev. a ad7013
C4C rev. a ad7013 absolute maximum ratings 1 (t a = + 25 c unless otherwise noted) v aa , v dd to gnd ......................... C0.3 v to +7 v agnd to dgnd ........................ C0.3 v to +0.3 v digital i/o voltage to dgnd ........... C0.3 v to v dd +0.3 v analog i/o voltage to agnd ........... C0.3 v to v dd +0.3 v operating temperature range industrial (a version) ................... C40 c to +85 c storage temperature range ............... C65 c to +150 c maximum junction temperature ...................+150 c ssop q ja thermal impedance ....................+122 c/w lead temperature soldering vapor phase (60 sec) ...........................+215 c infrared (15 sec) ..............................+220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions extended periods may affect device reliability. terminology sampling rate this is the rate at which the modulators on the receive channels sample the analog input. output rate this is the rate at which data words are made available at the rxdata pin. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the dac or adc transfer function. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the dac or adc. dynamic range dynamic range is the ratio of the maximum rms input signal to the rms noise of the converter, expressed logarithmically, in decibels (db = 20 log 10 [ratio]). signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the receive channel. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for a sine wave is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db settling time this is the digital filter settling time in the ad7013 receive section. bias offset error this is the amount of offset in the receive channel adc when the differential inputs are tied together. receive error vector magnitude this is a measure of the rms signal error vector introduced by the receive root-raised cosine digital filter. this is measured by applying an ideal transmit signal (i.e., an ideal p /4 dqpsk modulator and an ideal transmit root-raised cosine filter) to the receive channel and measuring the resulting rms error vector. offset vector magnitude this is a measure of the offset vector introduced by the ad7013 as illustrated in the figure below. the offset vector is calculated so as to minimize the rms error vector for each of the constellation points. error vector signal vector offset vector q i pin configuration v aa irx bypass agnd aux irx qrx aux qrx aux dac1 aux dac2 aux dac3 aux irx irx fs adjust agnd qrx v dd aux qrx mclk agnd dxclk mode1 data in rx frame frame in rx data dgnd rx clk frame out 13 1 2 5 6 7 3 4 8 9 10 11 12 14 18 28 27 24 23 22 26 25 21 20 19 17 16 15 top view (not to scale) ad7013 ordering guide model temperature range package option* ad7013ars C40 c to +85 c rs-28 *rs = ssop. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this device features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality.
rev. a ad7013 C5C pin function descriptions ssop pin number mnemonic function power supply 1v aa positive power supply for analog section. a 0.1 m f decoupling capacitor should be connected between this pin and agnd. 21 v dd positive power supply for digital section. a 0.1 m f decoupling capacitor should be connected between this pin and dgnd. both v aa and v dd should be externally tied together. 10, 25, 27 agnd analog ground. 16 dgnd digital ground. both agnd and dgnd should be externally tied together. analog signal and reference 28 bypass reference decoupling output. a 10 nf decoupling capacitor should be connected between this pin and agnd. 2, 4 irx, irx differential analog inputs for the i receive channel. these are the primary receive analog inputs and are selected by setting cr12 to a zero in the command register. 6, 8 qrx, qrx differential analog inputs for the q receive channel. these are the primary receive analog inputs and are selected by setting cr12 to a zero in the command register. 3, 5 aux irx, aux irx auxiliary differential analog inputs for the i receive channel. the auxiliary inputs are selected by setting cr12 to a one in the command register. 7, 9 aux qrx, aux qrx auxiliary differential analog inputs for the q receive channel. the auxiliary inputs are selected by setting cr12 to a one in the command register. 24 aux dac1 analog output from the 10-bit auxiliary dac. 3, 22 aux dac2, aux dac3 analog outputs from the 8-bit auxiliary dacs. 26 fs adjust an external resistor is connected from this pin to ground to determine the full- scale current for aux dac1, aux dac2, and aux dac3. serial interface and control 20 mclk master clock, digital input. when operating in is-54 digital mode this pin should be driven by a 6.2208 mhz cmos compatible clock source and 5.12 mhz clock source for analog mode. 19 dxclk transmit clock, digital output. this is a continuous clock equal to mclk/2 which can be used to clock the serial port of a dsp. 17 frame in digital input. this is used to frame the clocking in of 16-bit words for the control registers serial interface. 18 data in digital input. transmit serial data, digital input. this pin is used to clock in data for the serial interface on the rising edge of dxclk. 15 frame out digital output. this output represents a buffered version of frame in and is controlled by the mode1 pin. this pin can be used to daisy chain the frame in signal. 11 mode1 digital input. this pin determines the state of frame out. when mode1 is high, frame in is buffered and made available on frame out. when mode1 is low, frame out is in 3-state. receive interface and control 14 rxclk output clock for the receive section interface. 12 rxframe synchronization output for framing i and q data at the receive interface. 13 rxdata receive data, digital output. i and q data are available at this pin via a 16-bit serial interface. data is valid on the falling edge of rxclk. i and q data are clocked out as two 16-bits words, with the i word being clocked first. the last bit in each 16-bit word is a i/ q flag bit, indicating whether that word is an i word or a q word.
C6C rev. a ad7013 limit at parameter t a = C40 c to +85 c units description t 1 160 ns min mclk cycle time t 2 65 ns min mclk high time t 3 65 ns min mclk low time t 4 20 ns min mclk rising edge to dxclk rising edge propagation delay 60 ns max t 5 2t 1 ns dxclk cycle time t 6 t 1 C20 ns min dxclk minimum high time t 7 t 1 C20 ns min dxclk minimum low time t 8 25 ns min dxclk rising edge to frame in setup time t 9 10 ns min dxclk rising edge to frame in hold time t 10 16t 5 ns min frame in cycle time t 11 25 ns min dxclk rising edge to data in setup time t 12 10 ns min dxclk rising edge to data in hold time t 13 0 ns min frame in rising edge to frame out rising edge propagation delay 25 ns max t 14 25 ns max mode1 low to frame out 3-state t 15 25 ns max mode1 high to frame out active note 1 t 14 is derived from the measured time taken by the frame out pin to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 80 pf capacitor. this means that the time quoted in the timing characteristics is the (v aa = +5 v 10%; v dd = +5 v 10%; agnd = dgnd =0 v, f mclk = 6.2208 mhz; t a = t min to t max , unless otherwise noted) control serial interface timing 1 mxclk (i) dxclk (o) data in (i) note: (o) indicates an output, (i) indicates an input, mode1 = logic high mode1 (i) t 14 t 15 frame out (o) t 13 frame in (i) t 8 t 10 data db9 db8 db1 db0 a3 a0 s1 s0 address ignored t 11 t 12 t 4 t 1 t 2 t 3 t 9 t 6 t 7 3 ?state t 5 figure 2. 16-bit serial interface for writing to the ad7013 internal registers 1.6ma i ol c l 50pf to output pin +2.1v i oh 200 m a figure 1. load circuit for digital outputs
rev. a ad7013 C7C receive section timing (v aa = +5 v 10%; v dd = +5 v 10%; agnd = dgnd = 0 v,f mclk = 6.2208 mhz; t a = t min to t max , unless otherwise noted) mclk (i) rxclk (o) rxframe (o) rxdata (o) i msb i lsb 1 t 17 t 18 t 19 t 20 t 21 t 22 t 23 t 24 15-bit i word i/q flag bit 15-bit q word q lsb q msb 0 i/q flag bit q lsb dxclk (o) i msb final iq pair prior to power down cr14 note: (o) indicates an output, (i) indicates an input 0 i lsb 1 q msb the last dxclk edge which is used to write to command reg one, setting cr14 to one the last dxclk edge which is used to write to command reg one, setting cr14 to zero t 25 t 16 figure 3. receive serial interface timing with 4 sampling of the symbol rate (cr10 = 1) limit at parameter t a = C40 c to +85 c units description t 16 power-up receive to rxclk 10240t 1 ns max cr13 = 0, rx offset autocalibration on 6144t 1 ns max cr13 = 1, rx offset autocalibration off t 17 30 ns min propagation delay from mclk rising edge to rxclk rising edge 85 ns max t 18 2t 1 ns rxclk cycle time; cr10 = 1; 4 sampling of the symbol rate t 19 t 1 C20 ns min rxclk high pulse width; cr10 = 1 t 20 t 1 C20 ns min rxclk low pulse width; cr10 = 1 t 21 C10 ns min rxclk rising edge to rxframe rising edge 10 ns max t 22 32t 1 ns rxframe cycle time; cr10 = 1 t 23 2t 1 ns rxframe high pulse width; cr10 = 1 t 24 C10 ns min rxdata valid after rxclk rising edge 10 ns max t 25 10t 1 ns min dxclk rising edge to last falling edge rxclk 64t 1 ns max
C8C rev. a ad7013 limit at t a = parameter C40 c to +85 c units description t 26 power up receive to rxclk 10240t 1 ns max cr13 = 0; rx offset autocalibration on 6144t 1 ns max cr13 = 1; rx offset autocalibration off t 27 30 ns min propagation delay from mclk rising edge to rxclk rising edge 85 ns max t 28 4t 1 ns rxclk cycle time; cr10 = 0; 2x sampling of the symbol rate t 29 2t 1 C20 ns min rxclk high pulse width; cr10 = 0 t 30 2t 1 C20 ns min rxclk low pulse width; cr10 = 0 t 31 C10 ns min rxclk rising edge to rxframe rising edge +10 ns max rxclk to rxframe propagation delay t 32 64t 1 ns rxframe cycle time; cr10 = 0 t 33 4t 1 ns rxframe high pulse width; cr10 = 0 t 34 C10 ns min propagation delay from rxclk rising edge to rxdata valid +10 ns max t 35 12t 1 ns min dxclk rising edge to last falling edge of rxclk 128t 1 ns max t 36 2t 1 + 20 ns max 3-state to receive channel valid t 37 2t 1 + 20 ns max receive channel to 3-state relinquish time (v aa = +5 v 10%; v dd = +5 v 10%; agnd = dgnd =0 v, f mclk = 6.2208 mhz; t a = t min to t max , unless otherwise noted) receive section timing 1 t 37 is derived from the measured time taken by the receive channel outputs to change 0.5 v when loaded with the circuit of figure 1. the measured number is then extrapolated back to remove the effects of charging or discharging the 80 pf capacitor. this means that the time quoted in the timing characteristics is the true relinquish time of the part and as such is independent of external loading capacitance. mclk (i) rxclk (o) rxframe (o) rxdata (o) t 27 t 29 t 30 t 31 t 32 t 34 t 26 1msb dxclk (o) cr14 note: (o) indicates an output, (i) indicates an input 0 the last dxclk edge which is used to write to command reg one, setting cr14 to one the last dxclk edge which is used to write to command reg one, setting cr14 to zero t 35 t 28 q lsb 1lsb q msb 15-bit i word 1 i/q flag bit 15-bit i word i/q flag bit t 33 figure 4. receive serial interface timing with 2 sampling of the symbol rate (cr10 = 0) rxclk (o) rxframe (o) rxdata (o) t 36 dxclk (o) cr18 note: (o) indicates an output, (i) indicates an input the last dxclk edge which is used to write to command reg one, setting cr14 to zero t 37 the last dxclk edge which is used to write to command reg one, setting cr14 to one 3- state active 3- state figure 5. receive serial interface 3-state timing
rev. a ad7013 C9C register address register reset name a3 a2 a1 a0 size state description command 0 0 1 0 9 bits all zeros the command register is used to select various operating modes of the ad7013. a detailed description of the command register is given in table ii. vernier 0 1 0 0 4 bits all zeros the vernier register allows additional group delay to be introduced into the i and q adcs. this provides a means to vary the adc sampling instant. irx offset 0 1 0 1 10 bits all zeros the contents of the irx offset register are substracted from the i channel adc word. when autocalibration is selected, this register is automatically loaded by the ad7013 at the beginning of a normal operation. when user calibration is selected, this register can be externally loaded with a twos complement offset 10-bit word to be subtracted from subsequent adc samples. qrx offset 0 1 1 0 10 bits all zeros the contents of the qrx offset register are substracted from the q channel adc word. when auto calibration is selected, this register is automatically loaded by the ad7013 at the beginning of a normal operation. when user calibration is selected this register can be externally loaded with a twos complement offset 10-bit word to be subtracted from subsequent adc samples. aux dac1 0 1 1 1 10 bits all zeros the 10-bit auxiliary dac current output is determined by this register. the output current is equal to {aux dac1 full scale * n/2 10 } where n is the 10-bit word contained in the aux dac1 register and aux dac1 full scale is determined by the value of r set connected between fsadjust and agnd. aux dac2 1 0 0 0 8 bits all zeros the 8-bit auxiliary dac current output is determined by this register. the output current is equal to {aux dac1 full scale * n/2 8 } where n is the 8-bit word contained in the aux dac2 register and aux dac2 full scale is determined by the value of rset connected between fs adjust and agnd. aux dac3 1 0 0 1 8 bits all zeros the 8-bit auxiliary dac current output is determined by this register. the output current is equal to {aux dac3 full scale * n/2 8 } where n is the 8-bit word contained in the aux dac3 register and aux dac3 full scale is determined by the value of r set connected between fs adjust and agnd. reset 0 0 0 1 n/a n/a when this address in selected, all of the internal registers are initialized to their reset state. 6-bit load 0 0 1 1 n/a n/a when this address is used, a special loading sequence, as shown in table iv, is used to write to any of the internal registers. n/a 0 0 0 0 n/a n/a no action. n/a 1 1 1 1 n/a n/a no action. table i. description and address map for ad7013 internal registers irx offset adjust rx sampling vernier aux dac1 aux dac2 qrx offset adjust aux dac3 data in a3 ?a0 s1, s0 command register 6-bit load data buffer db9 ?db0 msb lsb 16-bit serial word figure 6. ad7013 registers
C10C rev. a ad7013 msb lsb command register one msb lsb rx sampling vernier register v3 v2 v1 v0 cr13 cr12 cr11 cr10 cr14 cr15 cr16 cr17 cr18 cr19 reserved msb lsb aux dac1 msb lsb aux dac2 aux dac3 d3 d2 d1 d0 d4 d5 d6 d7 d8 d9 d3 d2 d1 d0 d4 d5 d6 d7 figure 7. internal ad7013 registers cr10 = 0 low adc sample rate. the sample rate of the receive adcs are equal to 2 the symbol rate or equal to mclk/128. = 1 high adc sample rate. the sample rate of the adcs are equal to 4 the symbol rate or equal to mclk/64. cr11 = 0 rrc receive fir filter. this selects the root-raised consine filter response for the receive sigma-delta adcs. this is used to match the transmit rrc filter as required by the is-54 standard. the frequency response is shown in figure 16. = 1 analog mode fir filter. this selects a filter response which has a sharper roll-off than the rrc fir filter and the frequency response has also been scaled to operate at a master clock frequency of 5.12 mhz. this allows the sampling rate of the receive adcs to be a multiple of 10 khz as required for analog cellular. the frequency response is shown in figure 17. cr12 = 0 primary adc inputs. this selects irx and irx as the i channel inputs and qrx and qrx as the q channel inputs. = 1 auxiliary adc inputs. this selects aux irx and aux irx as the i channel inputs and aux qrx and aux qrx as the q channel inputs. cr13 = 0 auto adc offset calibration. if auto calibration is selected, then an offset word for both adcs is calculated each time the receive adcs are brought out of sleep mode. this allows adc offsets within the ad7013 to be automatically calibrated out. = 1 user adc offset calibration. when user calibration is selected, then contents of the offset registers are not updated by the ad7013 when brought out of sleep mode. this allows the user to load the offset register externally thereby allowing the ad7013 to also calibrate out external offsets. cr14 = 0 receive adc sleep mode. this enters the i and q adcs into a low power sleep mode after outputting the current iq sample. = 1 receive adc active mode. this activates the receive adcs for normal operation. cr15 = 0 8-bit aux dac3 sleep mode. this enters the 8-bit auxiliary dac into a low power sleep mode. = 1 8-bit aux dac3 active mode. this activates the 8-bit auxiliary dac for normal operation. cr16 = 0 8-bit aux dac2 sleep mode. this enters the 8-bit auxiliary dac into a low power sleep mode = 1 8-bit aux dac2 active mode. this activates the 8-bit auxiliary dac for normal operation. cr17 = 0 10-bit aux dac1 sleep mode. this enters the 10-bit auxiliary dac into a low power sleep mode. = 1 10-bit aux dac1 active mode. this activates the 10-bit auxiliary dac for normal operation. cr18 = 0 3-state enable. this enables the 3-state buffers on the receive serial interface. = 1 3-state disable. this disables the 3-state buffers on the receive serial interface, entering the serial interface into 3-state. cr19 = x no action. table ii. command register one
rev. a ad7013 C11C receive section the receive section consists of i and q receive channels, each comprising of a simple switched-capacitor filter followed by a 15-bit sigma-delta adc. the data is available on a 16-bit serial interface, interfacing easily to most dsps. on-board digital filters, which form part of the sigma-delta adcs, also perform system level filtering. a choice of two digital filter responses are available, optimized for either p /4 dqpsk digital mode or the existing analog cellular system. for digital mode, root-raised cosine digital filters can be selected; whereas for analog mode, digital filters with a C3 db point of 11.4 khz can be selected. their amplitude and phase response characteristics provide excellent adjacent channel rejection. a means is also provided to calibrate either on-chip or receive path offsets in both the i and q channels. the receive section is also provided with a low power sleep mode, drawing only minimal current between receive bursts. switched capacitor input the receive section analog front-end is sampled at mclk/4 by a switched-capacitor filter. the filter has a zero at mclk/8 as shown in figure 8a. the receive channel also contains a digital low-pass filter (further details are contained in the following section) which operates at a clock frequency of mclk/8. due to the sampling nature of the digital filter, the pass band is repeated about the operating clock frequency (mclk/8) and at multiples of the clock frequency (figure 8b). because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dbs (figure 8c) further simplifying the external antialiasing requirements. a simple r-c network can be used to attenuate the digital filter image at mclk/8 as shown in figure 9. mclk/8 mclk/4 mclk/2 mhz mhz mhz 0dbs 0dbs 0dbs ?0 dbs max front-end analog filter transfer digital filter transfer function system filter transfer function mclk/8 mclk/4 mclk/2 mclk/8 mclk/4 mclk/2 figure 8. switched capacitor and digital filter transfer functions a. b. c. receive channel differential inputs the receive channel uses differential inputs to interface more easily to iq demodulators and also to provide common-mode noise rejection. however, if required the receive channel inputs can also be configured for single ended operation. the primary and auxiliary channels have similar performance and either can be used for differential operation or single-ended operation. the cr12 control bit determines whether the primary or auxiliary inputs are connected to the differential inputs of the sigma-delta modulator. figure 9 illustrates an antialiasing filter comprised of a single pole rc network with a C3 db frequency of 159 khz. the low-pass filter provides sufficient rejection at images of the fir digital filter illustrated in figure 10c. for single ended operation, the inverting input should be con- nected to a bias voltage and the noninverting input should swing 1.3 v around this bias voltage in order to exercise the entire adc range. in applications where the full 1.3 v range is not required, the on-chip 1.23 v reference can be used to provide the bias voltage. for instance as in figure 10, an op295 rail-to-rail low power op amp is used to buffer the bypass pin in order to generate a 1.23 v bias . the v bias is connected to the inverting input thereby setting the single-ended input range equal to 0 v to 2.46 v. also with the addition of an attenuator circuit the input range can be expanded to 0 v to 4.92 v as shown on the second adc channel. if the inverting input is tied to agnd, then only half the adc range is available. ad7013 w 5k w w 5k w w 5k w w 5k w 0.01nf ir x qr x qr x ir x 10nf bypass i t q q iq demodulator 0.01nf figure 9. external rc network for differential signals ad7013 w 10k w w 10k w 0.1nf aux irx aux qrx aux qr x aux irx 0.1nf 10nf bypass w 10k w 0 to 4.92 volts 5v 1.23 volts 295 0 to 2.46 volts figure 10. external rc network for single-ended signals
C12C rev. a ad7013 v bias irx voltage v bias + 0.65 v bias ?0.65 irx adc code 10 ?00 00 ?00 01 ?11 figure 11. adc transfer function for differential operation v bias irx voltage v bias + 1.3 v bias ?1.3 irx adc code 10 ?00 00 ?00 01 ?11 sigma-delta adc the ad7013 receive channels employ a sigma-delta conversion technique, which provides a high resolution 15-bit output for both i and q channels with system filtering being implemented on-chip. the output of the switched-capacitor filter is continuously sampled at mclk/8, by a charge-balanced modulator, and is converted into a digital pulse train whose duty cycle contains the digital information. due to the high oversampling rate which spreads the quantization noise from 0 to f s /2, the noise energy which is contained in the band of interest is reduced (figure 13a). to reduce the quantization noise still further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (figure 13b). the digital filter that follows the modulator removes the large out of band quantization noise (figure 13c), while converting the digital pulse train into parallel 15-bit wide binary data. the 15-bit i and q data plus an i/q flag bit is made available, via a serial interface, as a 16-bit word, msb first. figure 12. adc transfer function for single-ended operation digital filter the digital filters used in the ad7013 receive section carry out two important functions. first, they remove the out of band quantiza- tion noise which is shaped by the analog modulator. second, they are also designed to perform system level filtering, providing the root-raised cosine filter as required for tia is-54. since digital filtering occurs after the a/d conversion process, it can remove noise injected during the conversion process. analog filtering cannot do this. also, the digital filter combines low passband ripple with a steep roll off, while also maintaining a linear phase response. this is very difficult to achieve with analog filters. filter characteristics the digital filter is a 256-tap fir filter, clocked at 1/8 the master clock frequency. a choice of two frequency responses are available: a root-raised cosine response (cr11 = 0) and a brick wall response at 11.4 khz (cr11 = 1) for analog mode. figure 16 and figure 17 illustrate the respective frequency responses for both digital mode and analog mode while figure 18 compares the low frequency response of the digital filters. due to the low-pass nature of the receive filters there is a settling time associated with step input functions. output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. hence, the ad7013 digital filters have a settling time of 256 8t 1 (i.e., 329.2 m s when mclk = 6.2208 mhz and 400 m s when mclk = 5.12 mhz). f s / 2 388.8khz quantization noise f s / 2 388.8khzmhz band of interest noise shaping band of interest f s / 2 388.8khz band of interest root raised cosine fir filter a b c figure 13. a. effect of high oversampling ratio. b. use of noise shaping to further improve snr. c. use of digital filtering to remove the out of band quantization noise a. b. c.
rev. a ad7013 C13C analog settling after power?p digital filter settling offset calibration receive channel in low power sleep mode normal operation digital filter settling power?p sequence analog settling cr14 rxframe rxclk 10240 x t 1 figure 14. autocalibration routine after exiting low power sleep mode analog settling after power?p digital filter settling receive channel in low power sleep mode normal operation calibration sequence cr14 rxframe rxclk 6144 x t 1 figure 15. user-calibration routine after exiting low power sleep mode
C14C rev. a ad7013 receive offset calibration included in the digital filter is a means by which receive signal offsets may be calibrated out. each channel of the digital low-pass filter section has an offset register. the offset register can be made to contain a value representing the dc offset of the preceding analog circuitry. in normal operation, the value stored in the offset register is subtracted from the filter output data before the data appears on the serial output pin. by so doing, dc offsets in the i and q channels get calibrated out. autocalibration or user calibration can be selected. autocalibration will remove internal offsets only while user calibration allows the user to write to the offset register in order to also remove external offsets. the offset registers have enough resolution to hold the value of any dc offset between 153 mv (1/8th of the input range). the 10-bit offset register represents a twos-complement value which is mapped to a 15-bit twos-complement word as shown in figure 19. the contents of the offset registers are subtracted from their respective adc samples. d0 d8 d2 d13 d14 d1 d0 10-bit i or q offset register 15-bit i or q offset word 0 0 msb lsb d9 d11 d12 d10 figure 19. position of the 10-bit offset word within the 15-bit adc word receive offset adjust: auto-calibration (cr13 = 0) if receive autocalibration has been selected (cr13 = 0), then the ad7013 will initiate an autocalibration routine each time the receive path is brought out of the low power sleep mode (cr14 = 0). the ad7013 internally disconnects the differential inputs from the input pins and shorts the differential inputs to measure the resulting adc offset. this is then averaged 16 times to reduce adc noise, and the averaged result is then placed in the offset register. the input to the adc is then switched back for normal operation, and after allowing for both analog settling and digital filter settling, the first iq sample pair is output (figure 14). autocalibration will only remove on-chip offsets. receive offset adjust: user calibration (cr13 = 1) when user calibration has been selected, the receive offset register can be written to, allowing offsets in the if/rf demodulation circuitry to be also calibrated out. however, the user is now responsible for calibrating out receive offsets belonging to the ad7013. when the receive path enters the low power mode (cr14 = 0), the offset registers remain valid. after powering up, the first iq sample pair is output once time has elapsed for both the analog circuitry to settle and also for the output of the digital filter to settle as shown in figure 15. frequency ?khz magnitude ?dbs 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 52.5 60.0 7.5 0.0 45.0 37.5 30.0 22.5 15.0 figure 16. receive root raised cosine fir filter; cr11 = 0, mclk = 6.2208 mhz frequency ?khz magnitude ?dbs 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 52.5 60.0 7.5 0.0 45.0 37.5 30.0 22.5 15.0 figure 17. receive analog mode fir filter; cr11 = 1, mclk = 5.12 mhz frequency ?khz magnitude ?dbs 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0.0 45.0 30.0 15.0 analog mode filter response digital mode filter response figure 18. comparision of the two frequency responses where digital mode was clocked at 6.2208 mhz and analog mode was clocked at 5.12 mhz
rev. a ad7013 C15C adc sampling vernier also included in the digital filter is the means to vary the sampling instant, as figure 20 illustrates. the absolute group delay can be varied from a minimum of four symbols to a maximum of four and a half symbols allowing the user to define the sampling instant to a resolution 1/32 of the symbol rate. the vernier can be used to seek the optimum sampling instant for minimum inter-symbol- interference (isi). vernier = n 0 n 15 vernier = 0 low sampling rate; cr10 = 0 sampling period = 128 x t 1 8 x t 1 x n vernier = 0 high sampling rate; cr10 = 1 sampling period = 64 x t 1 8 x t 1 x n vernier = n 0 n 7 time time figure 20. i and q adc sampling vernier for 2 the symbol rate and 4 the symbol rate a 4-bit vernier register is used to set the sampling instant for both the i and q receive adcs. when the vernier register is pro- grammed with zero the adcs will have a minimum group delay of approximately 165 m s. nonzero values in the vernier register will add additional group delay thereby moving the sampling instant for both adcs. after programming the sampling vernier it takes eight symbols ( ? 330 m s) for the digital filter to settle. when the adc is operating at the high rate, vernier values from 8 to 15 yield similar sampling instants as vernier values from 0 to 7, but delayed by an additional 1/4 of a symbol period. table iii. loading sequence for the 16-bit interface db9Cdb0 a3Ca0 s1, s0 action d9Cd0 destination address ignored destination reg ? d9Cd0 table iv. loading sequence for the 6-bit interface db9Cdb0 a3Ca0 s1, s0 action ignored 0011 d9, d8 d9 ? s1 and d8 ? s0 ignored destination address d7, d6 d7 ? s1 and d6 ? s0 ignored destination address d5, d4 d5 ? s1 and d4 ? s0 ignored destination address d3, d2 d3 ? s1 and d2 ? s0 ignored destination address d1, d0 d1 ? s1 and d0 ? s0 destination reg ? d9Cd0 receive section digital interface the receive interface can be connected to dsp processors requiring the use of only one serial port. the 15-bit i and q samples are made available as 16-bit words, where the last bit in each word is an i/q flag bit. the serial data is made available on the rxdata pin, with the i/q flag indicating whether the 16-bit word being clocked out is an i sample or a q sample. although the i data is clocked out before the q data, internally both samples are processed together. the receive interface (rxclk, rxframe & rxdata) can be 3- stated by setting cr18 to zero, cr18 should be set high for normal operation. when the receive section is put into sleep mode, by setting cr14 to zero, the receive interface will complete the current iq cycle before entering into a low power sleep mode. high sampling rate (cr10 =1) the timing diagram for the receive interface is shown in figure 3. the output word rate per channel is equal to 97.2 khz (mclk/64) which corresponds to 4 times the symbol rate. when the receive section is brought out of sleep mode (cr14 = 1), the receive section will initiate an offset autocalibration routine if cr13 = 0. once the receive offset calibration routine is complete then rxclk will continuously shift out i and q data, always beginning with i data. rxframe provides a framing signal that is used to indicate the beginning of an i or q, 16-bit data word that is valid on the next falling edge of rxclk. on coming out of sleep, rxframe goes high one clock cycle before the beginning of i data, and subsequently goes high in the same clock cycle as the last bit of each 16-bit word (both i and q). rxdata is valid on the falling edge of rxclk and is clocked out msb first, with the i/q flag bit indicating whether the 16-bit word is an i sample or a q sample. dxclk (o) data in (i) a3 frame in (i) note: (o) indicates an output, (i) indicates an input a2 a1 a0 ignored address db9 db0 data s1 s0 figure 21. 6-bit serial interface for internal ad7013 registers
C16C rev. a ad7013 pcb layout considerations the use of an analog ground plane is recommended, where the ground plane extends around the analog circuitry. both agnd and dgnd should be externally tied together and connected to the analog ground plane. good power supply decoupling is very important for best adc performance. a 0.1 m f ceramic decoupling capacitor should be connected between v aa and the ground plane. the physical place- ment of the capacitor (surface mount if possible) is important and should be placed as close to the pin of the device as is physically possible. this is also applied to the v dd pin. poor power supply decoupling can lead to a degradation in adc offsets and snr. the bypass pin should be decoupled to the ground plane using a 10 nf capacitor. large capacitor values are not recommended as this can cause the reference not to reach its final value, on power up, before adc autocalibration has commenced. capacitive loading of digital outputs should be minimized as much as possible if power dissipation is a critical factor. the charging and discharging of external load capacitances can be a significant contribution to power dissipation, especially when the ad7013 is in a low power sleep mode as the dxclk remains active. 10-bit aux dac1 agnd agnd agnd agnd 8-bit aux dac2 8-bit aux dac3 r set full?cale adjust control v ref (1.23v) ad7013 w 18k w w 4.5k w w 9k w w 9k w figure 22. aux dacs ad7013 aux dac1, aux dac2 or aux dac3 fs adjust 10nf bypass ? 1 to 4 volts +5v op-295 r load r fb r set 18k w aux dac r load r fb 10-bit w 2.4k w w 5.4k w 8-bit w 11k w w 4.9k w figure 23. external op amp circuitry to extend output voltage range low sampling rate (cr10 = 0) the timing diagram for the receive interface is shown in figure 4. the output word rate per channel is equal to 48.6 khz (mclk/ 128) which corresponds to two times the symbol rate. the low sampling rate operates in a similar manner to that described for the high sampling rate. auxiliary dacs one 10-bit auxiliary dac and two 8-bit auxiliary dacs are provided for extra control functions such as automatic gain control, automatic frequency control and power control. figure 22 illustrates a simplified block diagram of the auxiliary dacs. the aux dacs consist of high impedance current sources, designed to operate at very low currents while maintaining their dc accuracy. the dacs are designed using a current segmented architecture. the bit currents corresponding to each digital input are either routed to the analog output (bit = 1) or to agnd (bit = 0). each of the auxiliary dacs has independent low power sleep modes. the command register has three control bits cr17, cr16 and cr15 which control aux dac1, aux dac2 and aux dac3 respectively. a logic 0 represents low power sleep mode and a logic 1 represents normal operation. the full-scale currents of the auxiliary dacs are controlled by a single external resistor, r set , connected between the fs adjust pin and agnd. the relationship between full-scale current and r set is given as follows: 10- bit aux dac aux dac full scale ( ma ) = 7992 v ref ( v )/ r set ( w ) 8- bit aux dacs aux dac full scale ( ma ) = 3984 v ref ( v )/ r set ( w ) by using smaller values of r set , thereby increasing aux dac full- scale current, improved inl and dnl performance is possible as shown in table v. digital interface communication with the command register, auxiliary dacs, adc offset registers and adc vernier is accomplished via the 3-pin serial interface. either one of two loading formats may be used to write to any of the ad7013s internal registers. the first format consists of a single 16-bit serial word to write to any internal register (table iii). the second format consists of five 16-bit serial words, where only the last 6 bits in each 16-bit word are used to load five 2-bit data nibbles. the load sequence for this format is given is table iv. the second format is only enable when the register address 3 is used as the destination register as shown in table i. table v. aux dac1 inl and dnl as a function of r set 18 k w C1.45 +1.83 9 k w +1.22 +1.59 4.5 k w +1.18 +1.38 worst case worst case r set inl (lsbs) dnl (lsbs)
appendix 1 rev. a C17C 10-bit aux dac1 integral nonlinearities (inl) 8-bit aux dac2 integral nonlinearities (inl) 8-bit aux dac3 integral nonlinearities (inl) 10-bit aux dac1 differential nonlinearities (dnl) 8-bit aux dac2 differential nonlinearities (dnl) 8-bit aux dac3 differential nonlinearities (dnl) 0 1024 768 512 256 dac code 1.5 0 ?.5 1 0.5 ?.5 ? dnl error ?lsbs 0.5 0 ?.5 0 256 192 128 64 0.25 ?.25 dac code dnl error ?lsbs 0.5 0 ?.5 0 256 192 128 64 0.25 ?.25 dac code dnl error ?lsbs inl error ?lsb s 0.5 ?.5 0 ?.25 0.25 256 64 0 192 128 dac code 0.5 ?.5 256 0 ?.25 64 0 0.25 192 128 inl error ?lsb s dac code 1.5 ?.5 0 ? 256 ?.5 0 1 1024 768 512 dac code inl error ?lsb s 0.5 typical performance characteristicsCad7013
C18C rev. a ad7013 40 0 10 20 30 frequency ?khz magnitude db ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 40 0 10 20 30 frequency ?khz magnitude db ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 q channel digital mode fft; mclk = 6.2208 mhz p /4 dqpsk constellation diagram; typical error vector 2% rms p /4 dqpsk i and q receive samples i channel digital mode fft; mclk = 6.2208 mhz q channel analog mode fft; mclk = 5.12 mhz i channel analog mode fft; mclk = 5.12 mhz 48.6 0 12.15 24.3 36.45 frequency ?khz magnitude db ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 48.6 0 12.15 24.3 36.45 frequency ?khz magnitude db ?20 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 1 ? 0 0 ? 1 i samples q samples 1 ? 0 0 ? 1 i samples q samples
rev. a ad7013 C19C i channel adc noise histogram with irx and irx tied together and offset register = 0; number codes = 1000, standard deviation = 4.44 codes q channel adc noise histogram with qrx and qrx tied together and offset register = 0; number codes = 1000, standard deviation = 3.82 codes ad7013 sleep current as a function of dxclk load capacitance ?0 ?6 ?4 ?1 ?2 140 0 60 20 ?0 40 ?1 120 80 100 ?8 ?9 ?7 ?5 ?3 ?9 ?7 ?8 ?5 ?6 ?3 ?4 ?1 ?2 ?9 ?0 ?7 ?8 ?5 ?6 ?3 ?4 ?2 adc code number of occurrences ?0 ?6 ?4 ?1 ?2 140 0 60 20 ?0 40 ?1 120 80 100 ?8 ?9 ?7 ?5 ?3 ?9 ?7 ?8 ?5 ?6 ?3 ?4 ?1 ?2 ?9 ?0 ?7 ?8 ?5 ?6 ?3 ?4 ?2 adc code number of occurrences 50 0 200 150 100 dxclk load capacitance ?pf sleep mode i dd ?ma 3 0 1.5 0.5 1 2.5 2 v aa = v dd = +5v mclk = 6.2208 mhz cr14 = cr15 = cr16 = cr17 = 0
C20C rev. a ad7013 outline dimensions dimensions shown in inches and (mm). 28-lead ssop (rs-28) 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0 0.0256 (0.65) bsc 0.407 (10.34) 0.397 (10.08) 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) pin 1 15 14 1 28 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) printed in u.s.a. c1862aC7.5C7/94

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